The communication to and from both home and office is undergoing a change to provide both cable and DSL broadband access. It is highly desirable to provide a common computer/software/peripheral platform architecture across cable, DSL, IEEE 802.11, IP phone and voice gateways. A communications processor architecture includes a 32-bit MIPS processor, a switched bus architecture, a distributed DMA architecture, optimized memory interface, programmable memory management and write back or write through cache write policy. The software platform for the services includes device drivers (USB, PCI, Ethernet, HDLC, Timers, 802.11 etc.), RTOS support (VxWorks, Linux, Nucleus etc.), networking software (ATM, TCP/IP, bridging, routing, filtering etc.), network management (SNMP, web servers/stacks), PC drivers, and robust APIs with clearly defined software layers for customers to add value. A communications chip for all of these markets becomes costly. Texas Instruments Inc. built a product that has two DSPs for voice, many interfaces, a mixed signal processor, RAM, a MAC, a complete segmentation re-assembly (SAR) engine for ATM, HM interface, a broadband interface, memory interface and a VGA. The result is a product that has 256 pins and the chip becomes costly. This is also not very expandable because any expansion peripherals must be placed on the memory bus, which consumes memory bandwidth that is critical to the operation speed of the CPU. This also means that access to the peripheral is in the asynchronous cycle, which is slow as compared to DRAM. A 16-bit bus could be added with 32 pins but that is costly and would have a limited memory range. Many developers for products in these areas do not want to pay for such a costly chip with excess functionality. We have had to disable features on the chip but the customer still has to pay for features not used.
It is highly desirable to provide platforms for market segments wherein the main function is functionally integrated and an expansion capability is provided via a low cost, software compatible communications link.
Texas Instruments Incorporated provides for this by providing a serial, low pin count communications interface that enables the extension of an internal Common Bus Architecture (CBA) bus segment to one or more external physical devices. This is known as VLYNQ and it accomplishes this function by serializing bus transactions in one device, transferring the serialized transaction between devices via a VLYNQ port, and de-serializing the transaction in the external device. Multiple VLYNQ modules may be included on a single device such that VLYNQ devices are effectively daisy chained.
Referring to FIG. 1 there is illustrated a serial (i.e. low pin count) communications interface (VLYNQ) that enables the extension of an internal CBA (labeled VBUSP) bus segment to one or more external physical devices. VLYNQ accomplishes this function by serializing bus transactions in one device, transferring the serialized transaction between devices via a VLYNQ port, and de-serializing the transaction in the external devices. VLYNQ is a 3,5,7 or 9-pin serial interface for 1,2,3 or 4 bit parallel (serial but four bit wide) interface that allows one to connect peripherals that previously could not be directly connected to a communications processor. The devices have an internal bus (VBUS). VLYNQ is a serial interface that connects the internal bus of one device to an internal VBUS of another device. The internal VLYNQ accomplishes this function by serializing bus transactions in one device, transferring the serialized transaction between devices via a VLYNQ port, and de-serializing the transaction in the external device.
As illustrated in FIG. 1 the host communication processor 11 includes an internal VBUS (a virtual bus) 11a and a VLYNQ interface module 13 connected by a serial cable 12 to a peripheral such as a Texas Instruments Inc. C55x Voice DSP 15 that also contains a VLYNQ interface module 17 connected to VBUS 15a of DSP 15. The VBUS or virtual bus is internal to a semiconductor chip or device and provides the communications between modules on the chip or device using the chip or device standard protocols. The transmit pins on the first device 13 connect to the receive pins on the second device 17. Request packets, response packets, and flow information are all multiplexed and sent across the same physical pins. The above described connection between processor 11 and DSP 15 is a VLYNQ host-to-peripheral connection. A peer-to-peer connection is also provided. This enables the extension of an internal common bus architecture bus segment to one or more external physical devices. In FIG. 1 the first peripheral device (C55x Voice DSP) 15 includes a second VLYNQ interface module 19 connected to the internal VBUS 15a that is coupled by serial cable 14 to VLYNQ interface 20 at a second voice DSP 21 for a peer-to-peer connection. The second voice DSP 21 can be daisy chained to other DSPs or other peripherals via VLYNQ interface 23 and another cable.
An example of an application enabled by VLYNQ is a low cost derived voice application, allowing one or more C55x DSP devices to connect to an a Texas Instruments Inc. Avalanche Broadband Controller over 3-pin serial interfaces. For more information of VLYNQ, refer to application Ser. No. 10/382,679 filed Mar. 6, 2003 entitled “Communications Interface”. This application is incorporated herein by reference.
Successfully connecting VLYNQ devices requires an in-depth knowledge of the hardware module and accompanying register set. It is therefore highly desirable to provide a method to aid in connecting the devices.